Polycrystalline silicon (polysilicon) resistors are commonly used as load devices in a variety of digital and analog applications. Popular digital applications include semiconductor memory circuits such as Static Random Access Memories (SRAMs). FIG. 1 shows a conventional four device SRAM cell circuit referenced 1 with polysilicon load resistors. Two cross-coupled FETs T1 and T2, so-called the driver transistors, are connected between common node 2 tied to a first supply voltage Vs (usually the ground Gnd) and respective nodes 3 and 4, so-called charge storage nodes. These nodes 3 and 4 are connected to a common node 5 tied to a second supply voltage (usually a positive voltage Vc) respectively through load resistors R1 and R2. On the other hand, nodes 3 and 4 are also respectively connected to the bit lines BLT and BLC through FETs T3 and T4, so-called the access transistors. All FETs T1 to T4 are of the N type for best performance. The gates of the access transistors are connected to the word line WL, the potential of which controls FETs T3 and T4 for READ and WRITE operations. The circuit of FIG. 1 will be herein referred to as the 4D/2 R SRAM cell.
The flexibility that is offered by polysilicon load resistors in the design of the 4D/2R SRAM chip layout allows a significant reduction in the cell size, which in turn, results in a greater integration density. It is now a general practice in the industry to have the load resistors of 4D/2R SRAM cells formed by resistive polysilicon lands obtained from a very thin layer of either intrinsic or low doped polysilicon material. In addition, the polysilicon load resistors are stacked above the FETs for further increased integration density according to the advanced state of the art known to date. However, because these polysilicon load resistors must be fairly high-valued, say in the tera-ohms (10.sup.12 .OMEGA.) range, in order to decrease the current drawn by the cell, chip capacity appears to be limited to 1 megabits. Beyond 1 megabits, the polysilicon layer must be so thin that the process tolerances would be too difficult to control, consequently PFETs have to be used as load devices, but this is at the cost of a significantly more complicated manufacturing process.
FIG. 2 of the present application shows partial cross-sectional view of a typical structure of the prior art referenced 6, integrating the 4D/2R SRAM cell circuit of FIG. 1 with stacked polysilicon load resistors. Reference numeral 7 indicates the P type silicon substrate. Numerals 8 indicate the different field recess oxide (ROX) regions that are used to isolate the different active regions of the structure. Numerals 9 are active N+ implanted source and drain regions of the FETs. Numerals 10 indicate the gate dielectric layer, typically an SiO.sub.2 layer. The highly doped polysilicon gate electrodes of access FET T3 and driver FET T2 are respectively referenced 11-1 and 11-2. A polysilicon conductor referenced 11-3 is represented for sake of illustration. Conductor 11-3 overlies a ROX region 8 and makes an electrical contact with the source region 9 of FET T3. Gate electrodes 11-1 and 11-2 and conductor 11-3 result from the patterning of a first highly doped polysilicon layer 11 and they are covered by a thin insulating protective layer 12, except a small portion of gate electrode 11-2 which remains exposed. A small polycide (polysilicon converted in polysilicon silicide) land 13-1 is used to make a low resistivity interconnection between gate electrode 11-2, N+ drain region 9 of FET T3, and one end of load resistor R1 formed by a highly resistive polysilicon land 11-1. Polysilicon land 14-1 is obtained after patterning a second polysilicon layer 14 of either intrinsic or low doped polysilicon material. Polycide land 3-1 is typical of the local interconnect scheme at an early mask level that is conventionally used to provide short connections: e.g. from one active region of a FET to the polysilicon gate electrode of another FET or strap connections between two-adjacent active regions separated by a ROX region. Alternatively conductor 11-3 could be made of polycide instead of highly doped polysilicon as well. The resistive polysilicon land 14-1 is protected by top insulating layer 15. This top insulating layer 15 is relatively thick, say about 500-1000 nm and is generally made of phosphosilicate glass (PSG). As such, the structure results from the FEOL (Front End Of the Line) processing. At this stage of the process, the silicon wafer may be stored before personalization. Elements that will now be described are formed during the personalization steps or BEOL (Back End Of the Line) processing. Layer 15 is provided with contact openings to allow appropriate contacting with the bit lines, and power busses connected to either Vc or Gnd, through metal contacts that correspond to the M1 mask level. As apparent from FIG. 2, the other end of resistor R1 is connected to the said second supply voltage Vc via metal contact 16-1. Conductor 11-3 is connected to bit line BLT via metal contact 16-2.
FIG. 3 shows a cross-section of the structure of FIG. 2 taken along line I--I. FIG. 3 reveals in particular the implementation of driver FET T1 whose polysilicon gate electrode is referenced 11-4. Polysilicon land 14-2 forming load resistor R2 is located atop of it, but isolated therefrom by protective layer 12. Numeral 13-2 is another polycide land making a low resistivity interconnection between two active regions 9 separated by a ROX region 8.
Structure 6 depicted in FIGS. 2 and 3, that is obtained through a standard CMOS manufacturing process, exhibits some major inconveniences, mainly because the resistive polysilicon lands are formed during the FEOL processing steps. As apparent from FIGS. 2 and 3, all the succeeding layers are deposited conformally which results in the typical "corrugated" relief aspect of the upper metal/insulator structure. In particular, polysilicon load resistors (e.g. R1) formed by a polysilicon land (e.g. 14-1) have a very irregular shape. The top insulating layer 15 could be planarized as taught in "An advanced SA BICMOS technology for high performance 1 Mbits ECL I/O SRAMS" by W. R. Burger et all, IEEE proceedings IEDMP, p. 16.3.1 to 16.3.5, see in particular FIG. 1. However, this would necessitate a step of fellow at a relatively high temperature (about 800.degree.-900.degree. C.), that would change both the dopant distribution in the resistive polysilicon lands (e.g. 14-1) and polysilicon grain size thereof, which in turn, would modify value of the resistors (e.g. R1). It is a major characteristic of the structures of the prior art, to have the resistive polysilicon lands formed upon non-planar surfaces and before the PSG deposition takes place. In other words, the resistive polysilicon lands are fabricated during the FEOL, processing steps.
In addition, should the photolithographic step that is used to delineate the resistive polysilicon lands, e.g. land 14-2 atop the gate electrode 11-4 of FET T1, be subject to misalignment, this in turn, would result in a misregistration between land 14-2 and gate electrode 11-4. This point is illustrated in FIG. 3, where the offset of land 14-2 in land 14-2', as a result of said misregistration, is shown. As a consequence, the offset polysilicon land 14-2' is not only subject to the well known "step or edge coverage" effect which may result in a break of the land, but also to a significant change in the land section, thereby preventing load resistor R2 from attaining a value that is necessary for an appropriate operation of the circuit of FIG. 1. In addition, misregistration also results in poor reproducibility from chip to chip.
Another important point is the trimming of the resistive polysilicon lands during the wafer processing. This step is usually completed in CMOS standard processes by implanting dopants to trim the resistivity of the resistive polysilicon lands at the high resistance value that is desired and to ensure that a good matching between the pair of resistors of a same cell is obtained. With structure 6 of FIG. 2, this objective is difficult to attain because both polysilicon layer 14 and protective layer 12 are very thin, e.g. about 50-100 nm. Layer 14 must be thin to permit achievement of high value resistors, and layer 12 has to be thin enough not to create additional undesired relief in the upper metal/insulator structure. As a result, the implant energy must be accurately controlled. Otherwise, implantation dopants will contaminate underlying FETs. In addition, thinness of protective layer 12 creates a problem of modulation of the value of the resistor (e.g. R2) by the underlying polysilicon gate electrode (e.g. 11-4).
Finally, as explained above, the structure of FIGS. 2 and 3 capitalizes on the local interconnect conductive pattern scheme formed at an early mask level. It is well known that this pattern is limited to very short distance connections and at the vicinity of the surface of the silicon wafer. This limitation causes a serious problem to the circuit designer, particularly in multilevel chips. It is also apparent from FIG. 2 that the fragile polycide land 13-1 is also subject to the above mentioned "edge coverage" effect due to the sidewall sharpness of polysilicon gate electrode 11-2. Moreover, formation of polycide lands 13-1 and 13-2 also necessitates a specific photolithographic step.
As a result, for all the above mentioned reasons, the reliability of semiconductor structures integrating the 4D/2R SRAM cells manufactured according to standard CMOS processes as well as the inherent limitations thereof are not satisfactory in many respects.